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In order to test performance of the system, core operation of the system has been evaluated. The goal of the test were:
1. to check performance of context switch between two threads,
2. measure extra load introduced by critical section macros and system tick. <br.
The test consists of two threads and a semaphore, mutex, ISR working in different scenarios. Generally, the first thread (higher priority) was waiting on some object (semaphore or mutex) while the second thread or ISR releases the object. Delay was measured from release operation to continuation of execution in the thread that was waiting. Execution of testpoints in the code was signalled on output processor pins and recorded by logic analyser. The tests were carried out in two configuration:
(a) debug and verification features enabled (i.e. checking overflow, lock condition, statistics in scheduler, etc.)
(b) optimized for speed
| Id | Description | configuration (a) time [us] | configuration (b) time [us] |
| 1 | debug_pin_set debug_pin_clr | 0.16 | 0.16 |
| 2 | from os_sema_post() to release os_sema_wait() | 8.8 | 7.9 |
| 3 | from os_sema_post_intr() to release os_sema_wait() * | 10.48 | 9.26 |
| 4 | OS_DINT_SAVE OS_INT_RESTORE | 1.16 | 1.16 |
| 5 | os_schedule() and context switch | 3.59 | 3.2 |
| 6 | from os_mutex_release() to release os_mutex_get() | 8.94 | 7.86 |
| 7 | Tick ISR load (no timers) | 1.88 | 1.78 |
| 8 | Tick ISR load, 1 timer, not elapsed | 3.44 | 3.28 |
| 9 | Tick ISR load, 1 timer, elapsed, callback called. | 4.48 | 4.48 |
Measurements were performed on STM32L162 that run with 32MHz clock.
The code was compiled by GNU GCC with -O2.
(*) - Note that scheduling and context switch are performed in this case after finishing ISR execution.
Hence, this period includes ISR prolog instructions.
