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DioneOS News

Full verification of the system version for ARM Cortex-M3


Version for ARM Cortex-M3 was tested automatically (full code coverage: all functions, marcos, code lines, conditions, etc.). Tests were performed on STM32L162.

DioneOS for ARM Cortex-M3


DioneOS version for ARM Cortex-M3 processor was released.

Introduction to Multithreading


'Introduction to Multithreaded Programming' has been added in tutorials section

State Machine support.


State machine support has been added to the system. Pattern for state machine coding is defined.

Texas Instruments Developer Network


ELESOFTROM entered Texas Instruments MCU Developer Network. This program gathers companies that develop software for TI MCUs and provide professional services in this domain.

Regular MSP430 supported.


Support for regular MSP430 microcontroller and small code model has been added.

DioneOS release for MSP430x


First release of the DioneOS System. Support for MSP430x and large code model.

Testing protection of critical sections and behavior when an interrupt appears

In order to provide in-depth testing the DioneOS System in the time domain, its protection in critical sections and to confirm ARM Cortex-M3 behavior controlled interrupt forcing method was applied (figure below).

High resolution hardware timer was used in the tests. The timer was programmed to trigger interrupt after set delay. In this way it is possible to force the interrupt in specified program location. This type of test was executed mutiple time using consecutive value of the delay. An Address where interrupt appeared (see below stack image) together with other parameters were stored for each iteration. Such a test provided scanning critical location in the code and checking all possible cases (i.e. preemption because of different priorities, interrupt states including pending and active-pending one).

Determination of location where the interrupt appeared

After triggering the interrupt ARM Cortex-M3 stores on teh stack basic registers (i.e. XPSR, PC, R12, LR, R0-R3). They are stacked by hardware accoring to below image.

Using stack contents in ISR it is possible to determine return address and indirectly where the interrupt appeared. Additional test consists in LR register contents check that provides information if the interrupt is nested.

Advanced behavior of ARM Cortex-M3

During the tests used methods provided observation of advanced ARM Cortex-M3 bahavior:
- Tail-Chaining - omitting stacking registers in a case of next interrupt appering just after ISR (or pending because of priorities relation)
- Late Arriving Interrupt - higher priority interrupt that appears just before starting ISR of low priority interrupt.
- Regiter recovering from the stack - consecutive register recovering was observed
- Pipeline - some instructions are not yet effective at the consecutive one*.

*)-. If it needs to be avoided the barrier should be used.