ARMv7-M core is equipped with interrupt controller NVIC [Nested Vectored Interrupt Controller]. NVIC allows for 496 independent interrupts. The controller can be triggered by level on edge on its input line. NVIC uses exceptions (i.e. generalization of interrupt term) vector table and advanced mechanism for priorities. The priorities can be configured in various way providing flexible control over mutual preemption and their importance. Cortex-M3 core has additional hardware extensions that supports interrupts, i.e. stacking registers on interrupt entry, optimization in nesting case, etc.

I'am just explaining: ARMv7-M is an architecture type, its implementation is Cortex-M3 and STM32L is a type of microcontroller (a family) that has Cortexa-M3 core inside (among the core, the chip contains many interfaces, timers, FLASH memory, etc.).

The exception can be raised because of:

• intentional (present in code) execution of the instruction, e.g. SVC #n
• as a result of the system behavior
• when hardware interrupt appears
• breaking memory protection rules
• bus or alignment errors
• errors of core state
• debug events

It must be taken into consideration that ARMv7-M core differs from ARMv7 in servicing interrupts because of following items:

• performs hardware stacking the registers on ISR entry (on exit it restores the registers from stack)
• uses vector table of functions for exceptions handling
• exception are groupped in different way

• pending - exception is already raised but is not yet serviced by the core
• active - the core started servicing this exception but does not finished yet. Exception in this state can be preempted by another exception with higher priority.
• inactive - when exception is not in active nor pending state

Asynchronous exception (e.g. external interrupts) can be simultanously in active and pending state at the same time. This property provides that the exception is not lost if it is raised during execution of its ISR. Dzięki temu np. nie zostanie zgubione przerwanie zgłoszone podczas jego obsługi.

Each configurable priority consists of two parts (bit fields):
1. preemption group
2. sub-priority
The value of priority is no more than 8-bits wide (NOTE: STM32L has 4-bits wide priorities). Two parts of the priority provides control over exception preemption. When the core need to decide which exception should be handled first it follows the rules:

• priority with smaller value is more important
• exception can be preempted only by other exception from more important preemption group,
• if two interrupts are from the same preemption group, first handled is the one with more important subpriority (i.e. lower value)
• if two exceptions have the same priorities, first handled is the one with lower number (is located in exception table closer to begin of the table) - these numbers are fixed
• all configurable exceptions has priority 0

Before you start to assign priorities, you need to decide how to split n-bits priority into two parts.
For example STM32L can be configured as follows:

Case	Split	number of preemption groups	number of sub-priorities in the group	notes
1.	0:4	1	16	no preemption
2.	1:3	2	8
3.	2:2	4	4
4.	3:1	8	2
5.	4:0	16	1	each exception can be preempted

Required rules of preemption can be implemented by proper assigning exceptions to the groups and setting sup-priorities.

Example
Some embedded system based on STM32L uses 3 interrupts: EXTI0 (from external GPIO pin), USART1 (from USART, received/sent character) and TIM9 (Timer Interrupt). The requirement is that the exceptions from timer and usart should not preempt each other, and if are both pending usart interrupt should be handled first. We want that GPIO interrupt should has the highest priority and should preempt two former exceptions.

In order to satisfy these rules, the exception priorities can be configured as below:
* split the priority into group:sub-priority: 2:2
* priority EXTI0: 0.0 = 0
* priority USART1: 1.0 = 4
* priority TIM9: 1.1 = 5

An order of exceptions has two meanings:
- it defines which one is more important when two exceptions has the same priority
- defines exception location in exception vector table
Below you may find some part of exception list for STM32L1xx small and medium density devices

Priority	Nama	Description	Address	notes
-3	Reset	Reset	0x0000.0004	fixed priority
-2	NMI	non maskable interrupt	0x0000.0008	fixed priority
-1	HardFault	critical core errors	0x0000.000c	fixed priority
0	MemManage	memory manager	0x0000.0010
1	BusFault	fault at prefetch or memory access	0x0000.0014
2	UsageFault	undefined opcode or incorrect state	0x0000.0018
3	SVC_Handler	system service call by SVC	0x0000.002c
4	DebugMon	debug monitor	0x0000.0030
5	PendSV	request for pending system call	0x0000.0038
6	SysTick	system timer - periodic interrupt	0x0000.003c
7	WWDG	Window watchdog	0x0000.0040
..	...	...	0x0000.0044
13	EXTI0	interrupt from GPIO pin	0x0000.0058
..	...	...	0x0000.005c
17	EXTI4	interrupt from GPIO pin	0x0000.0068
18	DMA1_Channel1	DMA1 channel 1	0x0000.006c
..	...	...	0x0000.0070

Exceptions that comes from the core (Cortex-M3) are located at the begining of above list - they are highlighted in the table by darker color. According to naming in ARMv7-M documentation, PendSV and SysTick are external interrupts for the core.
NOTE: CMSIS library uses another numbering: IRQn <0 - processor exceptions, IRQn >= 0 - external exceptions (external for to the core).

When the ISR is finished registers are automatically restored from the stack.

Cortex-M3 has following types of barriers:
DMB - Data Memory Barrier
DSB - Data Synchronization Barrier
ISB - Instruction Synchronization Barrier